The ADF5002 is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input to a PLL IC, such as the ADF4156 or the ADF4106.
The ADF5002 prescaler provides a fixed divide‑by‑8 function for frequencies up to 18 GHz, delivering low phase‑noise output suitable for PLLs such as the ADF4156 or ADF4106. It operates from a single 3.3 V supply, offers differential 100 Ω RF outputs, and consumes 30 mA in active mode.
The datasheet includes specifications, absolute maximum ratings, pin descriptions, typical performance curves, and an evaluation‑board layout with bill of materials. It also provides an application circuit example for integrating the prescaler into a microwave PLL loop.
| Input Frequency Range | 4 GHz – 18 GHz |
|---|---|
| Supply Voltage | 3.3 V ±10 % |
| Phase Noise | −153 dBc/Hz (12 GHz, 100 kHz offset) |
| Output Power (single‑ended) | −10 dBm to −5 dBm |
| Output Voltage Swing (single‑ended) | 200 mV – 330 mV p‑p |
| Operating Temperature Range | −40 °C to +105 °C |
The device accepts input frequencies from 4 GHz to 18 GHz.
It operates from a single 3.3 V supply (±10 %).
The phase noise is −153 dBc/Hz at a 12 GHz input with a 100 kHz offset.