Freescale DSP56321 is a 24-bit digital signal processor that supports networking, security encryption, and home entertainment. It uses a high-performance single clock cycle per instruction engine, a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.
The Freescale DSP56321 is a 24‑bit digital signal processor designed for high‑performance, low‑power applications such as networking, security encryption, and home entertainment. It features a 275 MHz core, a 1.6 V core supply, 3.3 V I/O, and an optional Enhanced Filter Coprocessor (EFCOP) that can double its multiply‑accumulate throughput.
The datasheet details the device’s memory architecture, signal groups, packaging options, and power‑management features, and includes ordering information for the MAP‑BGA package variants. It also lists related documentation needed for full design implementation.
| Core clock frequency | 275 MHz |
|---|---|
| Core voltage | 1.6 V |
| I/O voltage | 3.3 V |
| MMACS performance | 275 million per second |
| MMACS with EFCOP | 550 million per second |
| Internal RAM total | 192 K × 24‑bit |
| Bootstrap ROM size | 192 × 24‑bit |
| Package type | MAP‑BGA |
| GPIO pins | up to 34 |
| DMA channels | 6 |
The DSP56321 operates with an internal 275 MHz clock.
It provides six DMA channels.
The device is offered in a MAP‑BGA (plastic‑ball grid array) package.
The core operates at 1.6 V.