The Freescale DSP56L307 is a 24-bit digital signal processor, a member of the DSP56300 DSP family, which supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations, enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance. Like the other DSP56300 family members, the DSP56L307 uses a high-performance, single-clock-cycle-per-instruction engine (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller. The DSP56L307 performs at up to 160 million multiply-accumulates per second (MMACS), attaining up to 320 MMACS when the EFCOP is in use. It operates with an internal 160 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power.
The Freescale DSP56L307 is a 24‑bit digital signal processor designed for networking, wireless, and high‑speed modem applications. It includes an Enhanced Filter Coprocessor (EFCOP) that can double the multiply‑accumulate performance to 320 MMACS while running at a 160 MHz internal clock.
The device is supplied in a MAP‑BGA package with 196 pins, operates on a 1.8 V core supply and 3.3 V I/O, and provides extensive peripheral interfaces such as HI08 host bus, dual ESSI ports, SCI, and a triple‑timer module.
| Maximum MMACS | 160 MMACS (320 MMACS with EFCOP) |
|---|---|
| Core Clock Frequency | 160 MHz |
| I/O Supply Voltage | 3.3 V |
| Package Type | Molded Array Plastic‑Ball Grid Array (MAP‑BGA) |
It can achieve up to 160 million multiply‑accumulates per second, or 320 MMACS when the EFCOP is enabled.
It is supplied in a molded array plastic‑ball grid array (MAP‑BGA) package.