This document introduces new information about the Motorola DSP56362 product, including its features and performance.
The DSP56362/D is a 24‑bit audio digital signal processor designed for digital audio compression, decompression, sound field processing, and equalization. It uses a high‑performance single‑clock‑per‑cycle DSP56300 core combined with Motorola Symphony™ DSP features, delivering up to 100 MIPS at a 100 MHz internal clock and 3.3 V supply.
Key features include a 56‑bit parallel barrel shifter, a fully pipelined 24 × 24‑bit multiplier‑accumulator, six DMA channels, on‑chip emulation (OnCE™), and a rich set of serial audio interfaces (ESAI, DAX, SHI). Memory resources are configurable, with up to 3072 × 24‑bit program RAM, 5632 × 24‑bit X‑data RAM, and optional external memory expansion up to 16 M × 24‑bit words. The device is offered in a 144‑pin LQFP package.
| Maximum instruction rate | 100 MIPS |
|---|---|
| Core clock frequency | 100 MHz |
| Barrel shifter width | 56‑bit |
| DMA channels | Six |
| Program RAM size | 3072 × 24‑bit |
| X‑data RAM size | 5632 × 24‑bit |
| Bootstrap ROM size | 192 × 24‑bit |
| Package type | 144‑pin LQFP |
The DSP56362/D can execute up to 100 MIPS using its internal 100 MHz clock.
It supports six DMA channels for internal and external memory accesses.
The device is supplied in a 144‑pin plastic thin quad flat‑pack (LQFP) surface‑mount package.