The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable wireless, telecommunications, and multimedia products.
The Freescale DSP56303 is a 24‑bit digital signal processor intended for telecommunications, audio, video and control applications. This document provides detailed technical data, including architecture features, memory configuration, peripheral interfaces and design considerations.
It includes specifications such as performance (100 MMACS at 100 MHz), power requirements, package options (144‑pin TQFP and 196‑pin MAP‑BGA), and signal pin descriptions to aid system designers in integrating the device.
| Maximum MMACS | 100 MMACS |
|---|---|
| Core Clock Frequency | 100 MHz |
| Core Supply Voltage | 3.0‑3.6 V |
| Internal RAM | 8 K × 24‑bit |
| Bootstrap ROM | 192 × 24‑bit |
| Package (TQFP) | 144‑pin TQFP |
| Package (MAP‑BGA) | 196‑pin MAP‑BGA |
The DSP56303 delivers 100 MMACS using an internal 100 MHz clock at 3.0‑3.6 V.
It is available in a 144‑pin TQFP package and a 196‑pin MAP‑BGA package.
The device includes 8 K × 24‑bit RAM total.
The core can run at up to 100 MHz.