128Mb F-die SDRAM Specification
This document provides the preliminary specifications for Samsung's 128Mb F-die CMOS SDRAM devices, covering the x4, x8, and x16 data‑bus configurations. It includes features such as JEDEC‑standard 3.3 V operation, LVTTL compatibility, four‑bank architecture, and programmable burst lengths and latencies.
Key sections detail the ordering information, package dimensions, functional block diagram, pin configuration, absolute maximum ratings, DC operating conditions, capacitance values, and command truth tables, giving designers a complete reference for integration of these memory parts.
| Supply voltage (VDD) | 3.0 V min / 3.3 V typ / 3.6 V max |
|---|---|
| Storage temperature | -55 °C to +150 °C |
| Power dissipation | 1 W |
| Package type | 54‑pin TSOP |
| Maximum operating frequency | 1.383 GHz (32M × 4) / 1.383 GHz (16M × 8) |
| Refresh period | 64 ms (4K cycles) |
| Input logic high voltage (VIH) | 2.0 V min / 3.0 V typ |
| Input logic low voltage (VIL) | -0.3 V min / 0 V typ / 0.8 V max |
| Clock pin capacitance | 2.5 pF min / 3.5 pF max |
| Data bus width options | x4, x8, x16 |
| Burst length options | 1, 2, 4, 8, Full page |
| CAS latency options | 2, 3 |
The device can be stored from –55 °C up to +150 °C.
It operates from 3.0 V minimum to 3.6 V maximum, with a typical value of 3.3 V.
All parts are supplied in a 54‑pin TSOP package.
The SDRAM is offered in x4, x8, and x16 configurations.