This document is about the technical data of SPRS079E. It mainly introduces its advanced multibus architecture, 40-bit arithmetic logic unit, 17 × 17-bit parallel multiplier, compare, select and store unit, exponent encoder, two address generators, data bus and extended addressing mode
The TMS320VC5402 is a fixed‑point DSP based on an advanced modified Harvard architecture with separate program and three data memory buses. It features a 40‑bit ALU, on‑chip ROM and RAM, and a rich set of on‑chip peripherals such as PLL, serial ports, timers and DMA.
The document provides a full description, pin assignments, terminal functions, electrical characteristics, timing diagrams, package options and revision history, enabling designers to integrate the device into new designs.
| ALU width | 40‑bit |
|---|---|
| On‑Chip ROM | 4K × 16‑bit |
| On‑Chip RAM | 16K × 16‑bit dual‑access |
| Instruction execution time | 10 ns (100 MIPS) at 3.3 V supply |
| Maximum external program space | 1M × 16‑bit |
| Package options | 144‑pin LQFP and 144‑pin BGA |
The device can address up to 1 M × 16‑bit external program space.
It is offered in a 144‑pin LQFP (PGE) and a 144‑pin BGA (GGU) package.
The DSP executes a fixed‑point instruction in 10 ns, delivering about 100 MIPS at a 3.3 V supply.
The TMS320VC5402 includes 4 K × 16‑bit on‑chip ROM.