The TMS320VC5421 digital signal processor is a dual‑core, 200‑MIPS fixed‑point device. Each core includes a 40‑bit barrel‑shifter, 40‑bit accumulators, and a 17‑bit × 17‑bit parallel multiplier. The processor provides 128 K‑word zero‑wait‑state on‑chip program memory shared between the two cores, plus 32 K‑word program/data DARAM, 32 K‑word data SARAM, and 2 K‑word ROM. It features three multichannel serial interfaces, two software‑programmable timers, two 8‑element FIFOs, and a 16‑bit host‑port interface (HPI).
Pin assignments and mechanical data are supplied for the 144‑pin Thin Quad Flat‑Pack (TQFP) and 144‑pin MicroStar ball‑grid‑array (BGA) packages. The datasheet also includes an important notice on product availability, warranty, and usage in critical applications.
| Performance | 200 MIPS |
|---|---|
| On‑chip program memory | 128 K‑word zero‑wait‑state shared memory |
| Package options | 144‑pin Thin Quad Flat‑Pack (TQFP) and 144‑pin MicroStar BGA |
| Serial interfaces | Three multichannel serial interfaces |
| Timers | Two software‑programmable timers |
| FIFOs | Two 8‑element FIFOs |
| Host‑port interface | 16‑bit HPI |
It is a dual‑core digital signal processor.
The device provides 128 K‑word zero‑wait‑state shared program memory.
It is offered in a 144‑pin Thin Quad Flat‑Pack (TQFP) and a 144‑pin MicroStar ball‑grid‑array package.
The processor runs at 200 MIPS.