Texas Instruments TMS320VC5410 Datasheet

The SPRS075D datasheet, published in October 1998, introduces the detailed information of the 565A chip, including its advanced multibus architecture, 40-bit arithmetic logic unit, 17- × 17-bit parallel multiplier, compare, select, and store unit, exponent encoder, two address generators, data bus, extended addressing mode, 64K x 16-bit on-chip RAM, 16K x 16-bit on-chip ROM, enhanced external parallel interface, etc.


Texas Instruments TMS320VC5410 Datasheet - cover page
Brand
Texas Instruments
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
79
File format
PDF
File size
1.2 MB
Published
28 March, 2012
Updated
01 October, 2023
MD5 checksum
A8805C5C7A7415E1A04EB833224A19EF

About this manual

The TMS320VC5410 is a fixed‑point digital signal processor featuring a 40‑bit ALU, 17‑bit parallel multiplier, and single‑cycle MAC operation. It offers separate program and data memory buses, on‑chip RAM and ROM, and a range of peripheral interfaces.

This datasheet includes a detailed product description, pin‑assignment tables for the 144‑pin PGE and 176‑pin GGW packages, terminal function tables, mechanical package data, and an important notice about warranty and product changes.

What's inside

  • Description
  • Pin Assignments
  • Terminal Functions
  • Oscillator/Timer Signals
  • Mechanical Data
  • Important Notice

Specifications

ALU width40‑bit
Parallel multiplier17‑bit
Multiply/Accumulate (MAC)Single‑cycle
I/O supply voltage3.3 V
Core supply voltage2.5 V
On‑chip RAM (additional)Seven blocks of 8K × 16‑bit
On‑chip ROM16K × 16‑bit
Maximum performance100–120 MIPS
PGE package pins144 pins

Frequently asked questions

What are the supply voltages for I/O and core operation?

The device uses a 3.3 V I/O supply and a 2.5 V core supply voltage.

How many pins are in the PGE package?

The PGE version of the TMS320VC5410 comes in a 144‑pin package.

What is the maximum MIPS performance of the TMS320VC5410?

The processor can achieve up to 100 MIPS and 120 MIPS depending on configuration.

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