This document mentions that TI's TUSB2046B, TUSB2077A and TUSB2036 chips have a small problem in determining the intended speed of an attached downstream device. According to the USB specification, the speed should be determined by sampling the DP or DM line following a 100ms debounce interval after either signal (DP or DM) first crosses the VIH threshold. The TUSB2046B (TUSB2077A, TUSB2036) actually samples the speed at the first VIH crossing and latches this value. This issue has only been observed recently with newer devices that either drive DM high or show excessive ringing during the initial connection, hence causing the speed detection to be seen as low speed by the TUSB2046B (TUSB2077A, TUSB2036).
The TUSB2046B (also TUSB2077A and TUSB2036) may incorrectly detect low‑speed operation for certain downstream devices due to a timing violation in the speed‑detection logic. The issue appears with newer devices that drive DM high or exhibit excessive ringing during initial connection, causing the controller to latch a low‑speed state.
TI recommends avoiding the problem by ensuring DP is asserted high before DM. If false low‑speed detection occurs, the software driver should issue a CLEAR_PORT_FEATURE(PORT_ENABLE) followed by a RESET_PORT after both DP and DM have stabilized.
| Affected controllers | TUSB2046B, TUSB2077A, TUSB2036 |
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Perform a CLEAR_PORT_FEATURE(PORT_ENABLE) followed by a RESET_PORT after DP and DM are stable.