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This document describes the features and characteristics of the 74HC/HCT237, which is a 3-to-8 line decoder/demultiplexer with address latches. It can be used for easy expansion or independent controls, and has features such as high speed, standard output capability, and low power consumption.

This document is a data sheet for the 74HC/HCT238 3-to-8 line decoder/demultiplexer. The product features demultiplexing capability, multiple input enable for easy expansion, and is ideal for memory chip select decoding. It has active HIGH mutually exclusive outputs with standard output capability. The IC is compatible with high-speed Si-gate CMOS devices and low power Schottky TTL (LSTTL). It accepts three binary weighted address inputs and provides 8 mutually exclusive active HIGH outputs. The decoder has three enable inputs for parallel expansion. It can be used as an eight output demultiplexer or a 1-of-32 decoder. The document also provides additional specifications and package information.

The 74HC/HCT240 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT241 is a high performance Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT241 is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE.

The 74HC/HCT243 is a high-speed Si-gate CMOS device with non-inverting 3-state bus compatible outputs, both in the send and receive directions. They are designed for 4-line asynchronous 2-way data communications between data buses.

This document describes the features and characteristics of the 74HC/HCT244 octal buffer/line driver.

The 74HC/HCT08 is a high-speed Si-gate CMOS device that is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT08 provide the 2-input AND function.

The document describes the features and characteristics of the 74HC/HCT10 triple 3-input NAND gate. They are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). The device provides the 3-input NAND function.

This document describes a 74HC/HCT107 dual JK flip-flop with reset, negative-edge trigger. It is a high-speed Si-gate CMOS device, pin compatible with low power Schottky TTL (LSTTL). It features standard output capability and flip-flop functionality.

The 74HC/HCT109 is a dual positive-edge triggered, JK flip-flop with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.

This document describes the features and characteristics of the 74HC/HCT11 triple 3-input AND gate, including output capability, power dissipation, propagation delay, and input capacitance.

This document describes the 74HC/HCT112 dual JK flip-flop with set and reset functions, which is triggered on the negative edge. The product has asynchronous set and reset functions, with standard output capability. It is suitable for high-speed Si-Gate CMOS devices and is pin compatible with low power Schottky TTL (LSTTL). It features dual JK flip-flops, as well as independent set and reset inputs. It complies with JEDEC standard no. 7A.

The 74HC/HCT123 is a dual retriggerable monostable multivibrator with reset. It is a high-voltage, high-output-drive device with Schmitt trigger action on all inputs except the reset input.

The 74HC/HCT125 is a high-speed Si-gate CMOS device with 3-state outputs. It has four non-inverting buffer/line drivers that can drive high load capacitances.

The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The HC/HCT126 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a HIGH impedance OFF-state.