This document describes the 74HC/HCT112 dual JK flip-flop with set and reset functions, which is triggered on the negative edge. The product has asynchronous set and reset functions, with standard output capability. It is suitable for high-speed Si-Gate CMOS devices and is pin compatible with low power Schottky TTL (LSTTL). It features dual JK flip-flops, as well as independent set and reset inputs. It complies with JEDEC standard no. 7A.
The document describes the 74HC/HCT112 as high-speed Si-gate CMOS devices that are pin compatible with low power Schottky TTL (LSTTL). These integrated circuits feature asynchronous set and reset capabilities, standard output capability, and are specified in compliance with JEDEC standard no. 7A.
The datasheet details the electrical characteristics for both HC and HCT variants across operating temperatures from -40°C to +125°C. It includes AC parameters such as propagation delay, clock pulse width, and maximum frequency, alongside DC input unit load coefficients. The document also lists ordering information for various package types including SOT109-1, SSOP338-1, DIP38-1, and TSSOP403-1.
| Maximum clock frequency (fmax) | 66 MHz (HC) / 70 MHz (HCT) |
|---|---|
| Input capacitance | 3.5 pF |
The device features negative-edge triggering.
Both the set (nSp) and reset (nRp) inputs are active LOW.