PHILIPS 74HC/HCT112 Dual JK flip-flop with set reset; negative-edge trigger handbook

Update: 29 September, 2023

This document describes the 74HC/HCT112 dual JK flip-flop with set and reset functions, which is triggered on the negative edge. The product has asynchronous set and reset functions, with standard output capability. It is suitable for high-speed Si-Gate CMOS devices and is pin compatible with low power Schottky TTL (LSTTL). It features dual JK flip-flops, as well as independent set and reset inputs. It complies with JEDEC standard no. 7A.

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MD5 Checksum: 80E643EE430ED08CE02622BE1B2D182F

Publication date: 02 July, 2012

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