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The 74HC/HCT390 is a high-speed dual 4-bit decade ripple counter. It has two BCD decade or bi-quinary counters, one package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100. Two master reset inputs can clear each decade counter individually. Output capability: standard. ICC category: MSI.
74HC/HCT160 is a high-performance Si-gate CMOS device that is pin compatible with low power Schottky TTL (LSTTL) and can be used for high-speed counting.
This document describes the features of the 74HC/HCT161 integrated circuit, including synchronous counting and loading, n-bit cascading count enable inputs, positive-edge triggered clock, asynchronous reset, etc. They are high-speed Si-gate CMOS devices that are pin compatible with low power Schottky TTL (LSTTL). They can be used for high-speed counting.
The 74HC/HCT165 is a high-speed Si-gate CMOS device that is pin compatible with low power Schottky TTL (LSTTL) and is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT165 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage.
This document describes the features and characteristics of the 74HC/HCT173 quad D-type flip-flop. It includes gated input enable for hold mode, gated output enable control, edge-triggered D-type register, asynchronous master reset, and output capability as a bus driver.
The 74HC/HCT174 is a high-speed, low-power CMOS device that is pin compatible with low power Schottky TTL (LSTTL). The device features six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs simultaneously load and reset (clear) all flip-flops. The register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output of the flip-flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.
This data sheet introduces the features and characteristics of the Philips Semiconductors 74HC/HCT191 Presettable synchronous 4-bit binary up/down counter
74HC/HCT193 is a presettable synchronous 4-bit binary up/down counter, which features synchronous reversible 4-bit binary counting, asynchronous parallel load, asynchronous reset, expandable without external logic, standard output, MSI category.
The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function.
