The 74HC/HCT109 is a dual positive-edge triggered, JK flip-flop with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.
The Philips 74HC/HCT109 is a high-speed Si-gate CMOS device featuring dual JK flip-flops with individual J, K, clock (CP), set (Sp), and reset (Rp) inputs. These devices are pin compatible with low power Schottky TTL (LSTTL) and are specified in compliance with JEDEC standard no. 7A.
The flip-flops operate as positive-edge triggered devices with asynchronous active LOW set and reset inputs. The J and K inputs allow the circuit to function as a D-type flip-flop, a toggle flip-flop, or in a 'do nothing' mode. Schmitt-trigger action in the clock input ensures high tolerance to slower clock rise and fall times.
| Propagation delay (nCP to nQ) | 15 ns (typical) |
|---|---|
| Maximum clock frequency | 75 MHz |
| Input capacitance | 3.5 pF |
| Power dissipation | 20 pW |
| Output capability | Standard |
The device is a dual positive-edge triggered JK flip-flop.
The set and reset inputs are asynchronous and active LOW.
Yes, by tying the J and K inputs together.