Industrial

The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

74HC/HCT138 is a 3-to-8 line decoder/demultiplexer with inverting function and mutually exclusive low level outputs

The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application.

This document describes the features and characteristics of the 74HC/HCT14 hex inverting Schmitt trigger. They are high-speed Si-gate CMOS devices and are compatible with low power Schottky TTL (LSTTL).

74HC/HCT147 10-to-4 line priority encoder datasheet introduces the features and characteristics of this product.

74HC/HCT153 is a high-speed Si gate CMOS device that is pin compatible with low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The two 4-input multiplexer circuits have individual active LOW output enable inputs (1E, 2E) which can be used to strobe the outputs independently. When the corresponding output enable inputs are HIGH, the outputs (1Y, 2Y) are forced LOW. The “153” is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0 and S1. The logic level S0 is high, and S1 is low when the multiplexer selects the output from D0 and D1; the logic level S0 is low, and S1 is high when the multiplexer selects the output from D2 and D3; the logic levels S0 and S1 are both high when the multiplexer selects the output from D4 and D5.

The 74HC/HCT154 decoders accept four active HIGH binary address inputs and provide 16 mutually exclusive active LOW outputs.

The 74HC/HCT157 are high-speed Si-gate CMOS devices with non-inverting data path. The device has standard output capability and belongs to the MSI category.

This document describes a quad 2-input multiplexer called 74HC/HCT158, which has an inverting data path and standard output capability. It can select 4 bits of data from two sources and is controlled by a common data select input (S). The four outputs present the selected data in the inverted form. Moving the data from two groups of registers to four common output buses is a common use of the '158'. It can also be used as a function generator, allowing the implementation of highly irregular logic. The product complies with JEDEC standard 7A.

74H1G66 is a CMOS single bidirectional switch with high speed and low power consumption.

This is a document introducing the characteristics of the HCMOS 74HC/HCT/HCU series logic circuits

The 74HC/HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT00 provide the 2-input NAND function.

This document describes the features and characteristics of the 74HC/HCT02 quad 2-input NOR gate.