This document describes a 74HC/HCT107 dual JK flip-flop with reset, negative-edge trigger. It is a high-speed Si-gate CMOS device, pin compatible with low power Schottky TTL (LSTTL). It features standard output capability and flip-flop functionality.
This document is a product specification datasheet for the 74HC/HCT107 integrated circuit. The device consists of two high-speed Si-gate CMOS JK-type flip-flops that are pin compatible with low power Schottky TTL (LSTTL). It features individual J, K, clock, and reset inputs along with complementary Q outputs.
| Output capability | standard |
|---|---|
| Loc category | flip-flops |
| Supply voltage range (74HC) | -40 to +85 Vcc |
It is a dual negative-edge triggered JK-type flip-flop.
The reset (nR) is an asynchronous active LOW input that overrides the clock and data inputs.