PHILIPS 74HC/HCT107 Dual JK flip-flop with reset; negative-edge trigger datasheet

Update: 28 September, 2023

This document describes a 74HC/HCT107 dual JK flip-flop with reset, negative-edge trigger. It is a high-speed Si-gate CMOS device, pin compatible with low power Schottky TTL (LSTTL). It features standard output capability and flip-flop functionality.

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Publication date: 02 July, 2012

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