ATMEL Manuals

This document introduces the Atmel XMEGA clock system, including internal and external oscillators, crystal oscillator failure monitor, high frequency phase locked loop and clock prescalers.

This document introduces the features and characteristics of XMEGA DAC in the AVR1508 Xplain training, including configuration options and functionality, conversion triggers, and single and dual channel operation.

Introduces the low power features of Atmel XMEGA microcontrollers, including various sleep modes and software controlled clock gating, and details how to shut down unused peripheral clocks in both normal operation mode and sleep mode.

This document describes the basic features and use of the Atmel XMEGA USART, including polled mode, interrupt mode and DMAC mode

The document describes the firmware features of the Xplain Board Controller, including USB interface, mass-storage and Atmel AVR XMEGA TM reset control.

Introduces Atmel picoPower technology and picoPower Board, and describes the picoPower function of ATmega48PA, ATxmega32A4 and AT32UC3L064

This document discusses the advantages of Atmel's megaAVR family of microcontrollers in terms of reducing time-to-market and improving production efficiency. It describes the development tools, on-chip resources, efficiency for high level languages, and fast and reliable programming capabilities of this microcontroller family.

JTAGICE mkII is Atmel's on-chip debugging tool for the AVR® microcontroller family. It supports debugging with AVR's traditional JTAG interface and with the debugWIRE interface. The JTAGICE mkII supports PC communication via RS-232 and USB. It is supported by AVR Studio version 4.09 and later. When connecting to the target board through the debugWIRE interface, only the RESET pin is used for communication. To enable the debugWIRE interface on an AVR Device, the debugWIRE Enable fuse, DWEN, must be programmed (DWEN=0). AVR devices with debugWIRE interface are shipped with the DWEN fuse unprogrammed. ISP or High-Voltage Programming is required to enable debugWIRE. Programming the fuse via ISP requires an ISP header on the target board. Using the 6-pin ISP header as shown in Figure 1 is recommended. The JTAGICE mkII supports ISP as a general programming interface, as well as having built-in support for handling the DWEN fuse and performing the Chip Erase when debugging. ISP is also supported by Atmel's STK500 and AVRISP mkII. See the relevant user guides for more information. All user guides are found in the AVR Studio Online help. The recommended connection when the JTAGICE mkII is used for both debugWIRE and limited ISP is the ISP6PIN header. See Figure 1, Figure 2 on page 2, and Table 1 on page 2.

This document introduces the features and characteristics of the ATmega162 microcontroller, including high performance, low power, high endurance non-volatile memory segments, JTAG (IEEE std. 1149.1 Compliant) interface, boundary scan capabilities, extensive on-chip debug support, two 8-bit timers/counters, one 16-bit timer/counter, real time counter, four PWM channels, 8-channel, 10-bit ADC 8 single-ended channels 7 differential channels in TQFP package only 2 differential channels with programmable gain(1x, 10x or 200x), byte-oriented two-wire serial interface, programmable serial USART, master/slave SPI serial interface, programmable watchdog timer

This is a PDF file about ATmega8A microcontroller. ATmega8A is a high performance, low power AVR® 8-bit microcontroller. It has advanced RISC architecture, 131 powerful instructions, most single clock cycle execution, 32 x 8 general purpose working registers, fully static operation, up to 20 MIPS throughput at 20 MHz, on-chip 2-cycle multiplier.

This document describes a high-performance, low-power AVR 8-bit microcontroller with features such as RISC architecture, nonvolatile program and data memories, peripheral features, special microcontroller features, and I/O and packages.

This document introduces the features of the ATmega32A series of 8-bit MCUs, including high performance, low power consumption, a large number of channels, extensive functions, and flexible expandability.

ATtiny24/44/84 is a high-performance, low-power AVR® 8-bit microcontroller with an advanced RISC architecture that can execute 120 powerful instructions, most of which are executed in a single clock cycle. It has 32 x 8 general-purpose working registers and fully static operation. ATtiny24/44/84 has 2/4/8K bytes of In-System Programmable Program Memory Flash (ATtiny24/44/84), endurance of 10,000 write/erase cycles; 128/256/512 bytes of In-System Programmable EEPROM (ATtiny24/44/84), endurance of 100,000 write/erase cycles; 128/256/512 bytes of internal SRAM (ATtiny24/44/84); and programmable locking for self-programming Flash program and EEPROM data security.

This document describes the features of the ATmega8515L/ATmega8515 microcontrollers, including RISC architecture, nonvolatile program and data memories, peripheral features, special microcontroller features, I/O and packages.