Key facts
- Brand
- Micrel
- Model
- SY100S839V
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-06-07
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Micrel SY100S839V Clock Generation Chip Datasheet
The Micrel SY100S839V is a low skew clock generation chip designed explicitly for applications requiring precise alignment of common output edges. It supports both differential and single-ended ECL/LVECL or PECL/LVPECL input signals and can be driven by 3.3V or 5V power supplies.
The device features internal dividers that are synchronous to each other, ensuring all output edges are precisely aligned. Key characteristics include a maximum output-to-output skew of 50ps and 50% duty cycle outputs. The chip includes a synchronous enable/disable function and an internal master reset for synchronization.
Micrel SY100S839V specifications
| Output-to-Output Skew | 50ps |
|---|---|
| Duty Cycle Outputs | 50% |
| Power Supply Options | 3.3V and 5V |
| Maximum Toggle Frequency | 1000 MHz |
| Package Type | 20-pin SOIC |
All Micrel SY100S839V documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the maximum toggle frequency of the SY100S839V?
The maximum toggle frequency is 1000 MHz.
What power supply options are supported?
The device supports both 3.3V and 5V power supply options.
What power‑supply voltages are supported by the SY100S839V?
The chip can be powered from either a 3.3 V or a 5 V supply.
How does the common enable (/EN) function?
The /EN input is synchronous and only enables the internal dividers when the internal clock is already low, preventing runt pulses.