This user guide describes the sld_virtual_jtag Megafunction, a virtual JTAG programming module which can be used as an IP core to implement JTAG programming in Altera FPGAs.
The Virtual JTAG (SLD_VIRTUAL_JTAG) megafunction provides access to the JTAG input pins and control signals from the JTAG controller on Altera devices. It acts as a general-purpose serial communication interface, allowing users to develop custom applications and debugging tools during runtime. The guide details how to use this feature within the Quartus II software on-chip debugging tool suite.
The megafunction supports the Arria, Stratix, Cyclone, HardCopy ASICs, MAX II, and APEX II, APEX 20KE, and APEX 20KC series.
The interface requires Test data in (TDI), Test data out (TDO), Test mode select (TMS), and TCK.