This document introduces the BDMA Usage on 100 pin ADSP-218x DSPs configured for IDMA use.
This document explains how to configure and use the Block Data Move Accelerator (BDMA) on 100-pin ADSP-218x processors that are set up for IDMA (Internal DMA) mode. In this configuration, the memory interface is partially functional, but the BDMA interface remains usable with specific limitations, such as a 20-bit address space and approximately 8 cycles of overhead per word transferred in blocks up to 256 DM words or 170 PM words.
The guide details a method to generate up to 20 bits of address by combining specific pins and address bits, allowing the transfer of up to 1 Megabyte. It provides example assembly source code demonstrating block transfers between internal memory (DM/PM) and external memory (BM), including routines for setting up control registers and handling interrupts to manage sequential transfers without crossing 512-byte boundaries.
| Address Space | 20 Bits |
|---|---|
| Overhead per DM word | Approx. 8 cycles |
| Max DM words per block | 256 words |
| Max PM words per block | 170 words |
| Processor Pin Count | 100 pin |
There is approximately 8 cycles of overhead per DM or PM word transferred in blocks of up to 256 DM words or 170 PM words.
Yes, the BDMA interface can still be used in IDMA mode, albeit in a somewhat limited way.
Up to 20 bits of address can be generated for use with the BDMA function.