This document describes the salient features of the ADSP-219x processor's six-stage instruction pipeline, which includes Look-ahead, Pre-fetch, Fetch, Address generation, Decode, and Execute stages. It explains that while this is not an execution pipeline (the core executes in a single cycle), the additional depth allows for increased operating speed by keeping up to 6 instructions in different stages of completion.
| Pipeline Stages | six-stage instruction pipeline |
|---|---|
| Core Execution Cycles | single core cycle |
| Memory Pipeline Depth | two-stage memory pipeline |
| Data Availability Latency | two core cycles |
During any given cycle, up to 6 instructions may be in different stages of completion.
There is a minimum pipeline latency of 4-cycles in servicing an interrupt.
If the branch is not taken, there is no latency introduced by the instruction pipeline.