Interfacing NAND Flash Memory with ADSP-21161 SHARC Processors Application Note

About this manual

This document provides technical guidance on interfacing NAND flash memory with the Analog Devices ADSP-21161 SHARC processor. It addresses the fact that this specific processor does not have an integrated NAND flash controller, requiring external interface design.

The note details two different interfacing schemes to provide flexibility for system designers and includes validated code examples in both C and assembly languages. Specific hardware components used for demonstration include the K9F1208U0B NAND Flash from Samsung Electronics.

What's inside

• Introduction
• NAND Flash versus NOR Flash
• Overview of the ADSP-21161 Processor's External Port
• K9F1208U0B NAND Flash Specifications
• NAND Flash Interface Signals
• Flash Commands Overview
• READ Operation Timing
• Program Operation Timing
• Block Erase Operation

Specifications

Frequently asked questions

What languages are used for the code examples?

The code examples provided in the document are in C and assembly languages.

What is the typical time required to erase a 16-Kbyte block?

An erase operation can be performed in 2 ms (typical) on a 16-Kbyte block.

What is the typical cycle time per byte for reading data from the page?

Data in the page can be read out at 50 ns (60 ns for K9F1208R0B) cycle time per byte.

How many bytes constitute a single page in the K9F1208U0B device?

One page consists of 528 bytes.