Analog Devices Video Framework Considerations for Image Processing on Blackfin Processors EE-276

About this manual

This Engineer-to-Engineer Note (EE-276) provides technical guidance on memory partitioning and data flow management for multimedia framework design using Analog Devices Blackfin processors. It specifically addresses the ADSP-BF533 and ADSP-BF561 models, focusing on maximizing system efficiency through hierarchical memory usage and non-intrusive DMA with the Parallel Peripheral Port interface.

The document details strategies for optimizing internal L1 memory allocation and SDRAM memory space to minimize latency during simultaneous core and DMA accesses. It also covers DMA modes for PPI capture and display, including handling ITU-R-656 input modes, managing external data accesses, and implementing de-interlacing techniques to achieve real-time video processing without frame loss.

What's inside

• Introduction
• Memory Considerations
• Internal Memory Space
• SDRAM Memory Space
• Managing External Data Accesses
• DMA Modes for PPI Capture and Display
• Working with ITU-R-656 Input Modes
• De-interlacing Using Memory DMA

Frequently asked questions

Which processor models does this application note cover?

This document provides considerations for the ADSP-BF533 and ADSP-BF561 Blackfin family processors.

What is the size of each subsection in the L1 data SRAM?

Each subsection in the L1 data SRAM consists of 4 Kbytes of memory.

How many internal banks does the SDRAM controller support?

The SDRAM controller supports a connection to four internal banks within the SDRAM.