This document describes the SPI slave booting function of SHARC® processors
The document addresses a complication in using the SHARC processor's SPI slave boot scheme where the protocol lacks a mechanism for the slave to pause the host transmission. This causes potential data loss if the processor executes code (zero-initialization loops) while the host continues streaming data, leading to an overflow of the 2-deep SPI FIFO.
To resolve this, the note provides two solutions: a hardware method using a feedback signal via a FLAG pin or the MISO pin to pause the host, and a software method where the SPI host reads initialization headers in the .LDR file to throttle the boot stream based on zero-initialization sections.
The document applies to all SHARC processors that support SPI slave boot: ADSP-2116x, ADSP-2126x, ADSP-2136x, and ADSP-2137x.
Overflow occurs when the processor executes zero-initialization loops for too long while the host continues transmitting data.
The SPI host reads initialization headers from the .LDR file and pauses transmission after sending a header if it indicates a zero-initialization section.