Understanding Jitter Requirements of PLL-Based Processors EE-261

About this manual

This document serves as a technical guide for hardware design engineers responsible for selecting components that satisfy the clock jitter requirements of PLL-based processors. It specifically focuses on the ADSP-TS201S TigerSHARC processor but provides general definitions applicable to other systems.

The text defines three primary ways to characterize jitter: period jitter, cycle-to-cycle jitter, and time interval error (TIE). It explains that while processor manufacturers often care about period jitter regarding guard-banded frequency specs, they may use TIE measurements in laboratory setups. The document also addresses the discrepancy where clock driver manufacturers typically specify cycle-to-cycle jitter.

What's inside

• Introduction
• Terminology
• Jitter Examples
• Statement of the Problem
• Jitter Frequency Domain Transfer Function

Frequently asked questions

What processor model does this application note specifically analyze?

The document analyzes the ADSP-TS201S TigerSHARC processor.

What is the maximum allowed period shrinkage for the ADSP-TS201S before failure?

The clock period can shrink by 40 ps before it violates the processor's guard-banded frequency spec.

What base clock frequency and PLL multiplier are used for the jitter transfer function example?

The example uses a base clock of 125 MHz with the PLL multiplier set to 4.