ANALOG DEVICES Understanding Jitter Requirements of PLL-Based Processors Manual

Update: 30 September, 2023

This EE-Note describes jitter requirements of PLL-based processors, including data-clock jitter in synchronous protocols and signal jitter in CDR (clock data recovery) applications.

File format: PDF

Size: -

MD5 Checksum: FEF6F5BA93459706D1A7919B80730238

Publication date: 03 August, 2012

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PDF Link: ANALOG DEVICES Understanding Jitter Requirements of PLL-Based Processors Manual PDF

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