ANALOG DEVICES Understanding Jitter Requirements of PLL-Based Processors Manual

This EE-Note describes jitter requirements of PLL-based processors, including data-clock jitter in synchronous protocols and signal jitter in CDR (clock data recovery) applications.


Brand
Analog Devices
File format
PDF
Published
03 August, 2012
Updated
30 September, 2023
MD5 checksum
FEF6F5BA93459706D1A7919B80730238
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