Altera EPXA1 I/O Pins Handbook

EPXA1 I/O Pins version 1.6 is a product released by Altera Corporation. It has two packaging forms: 672-Pin FineLine BGA and 484-Pin Fineline BGA. It supports DDR_VS0, DDR_VS1 and other functions.

Brand: Altera
Category: Other Electronics
Document type: Datasheet
Language: English
Pages: 15
File format: PDF
File size: 36 KB
Published: 01 August, 2012
Updated: 01 October, 2023
MD5 checksum: A7244A17B738C70F025C30FD5A37A533
PDF: Altera EPXA1 I/O Pins Handbook PDF

About this manual

This document serves as a technical reference for the Altera EPXA1 FPGA, specifically focusing on the I/O pin configurations. It provides a comprehensive list of pin assignments across various banks, including power connections (VCCIO, GND_IO) and specific signal functions.

What's inside

Pad Number
Bank
VCCIO
GND_IO
SD_DQ
DDR_VSO
VCC_INT
GND_INT
UART
EBI

Specifications

Pin Count	672-Pin
Alternative Pin Count	484-Pin
Document Version	version 1.6

Frequently asked questions

What is the function of pin B2-6?

Pin B2-6 functions as SD_DQ0.

Where are pins VCCIO and GND_IO located in Bank B2?

VCCIO is at pin B2-7 and GND_IO is at pin B2-8.

What are the functions of pins B3-304 and B3-305?

Pin B3-304 is VO, CLKUSR(1) and pin B3-305 is VO, RDYnBSY (1).

Download PDF (36 KB)