Describes the high-speed source-synchronous differential I/O interfaces in Altera Stratix GX devices, introduces the DPA feature, and compares DPA with CDR
The document addresses the challenge of managing skew between clock and data signals in high-speed telecommunications systems. It introduces Dynamic Phase Alignment (DPA), a feature embedded in the Stratix GX family of FPGAs, which eliminates this skew to increase system efficiencies and bandwidth without requiring fixed training patterns or higher power consumption associated with individual analog PLLs.
The dynamic phase aligner supports differential I/O standards at speeds up to 1 Gbps with DPA.
No, unlike previous devices, you do not have to use a fixed training pattern with DPA in Stratix GX devices.
The dynamic phase aligner supports LVDS, LVPECL, and 3.3-V PCML I/O standards.