Cyclone V FPGAs are designed to simultaneously meet shrinking power consumption, cost, and time-to-market requirements and increasing bandwidth requirements for high-volume, cost-sensitive applications. Built on TSMC’s 28-nm Low-Power (28LP) process and including an abundance of hard IP, Cyclone V FPGAs deliver up to 40% lower power compared to the previous version.
The Altera Cyclone V FPGA family is designed to meet requirements for shrinking power consumption, cost, and time-to-market while increasing bandwidth. Built on TSMC's 28-nm Low-Power (28LP) process, these devices offer up to 40% lower power compared to the previous generation and include an abundance of hard IP.
The family is divided into three targeted variants: Cyclone V E for general logic and DSP applications, Cyclone V GX for 614 Mbps to 3.125 Gbps transceiver applications, and Cyclone V GT for 5.0 Gbps transceiver applications. Key features include new 8-input adaptive logic modules (ALM), up to 12M of memory, variable precision DSP blocks, and support for 3G and 5G serial transceivers.
| Process Technology | 28-nm TSMC low-power process technology |
|---|---|
| Core Voltage | 1.1-V |
| Transceiver Data Rate | 614 Mbps to 5.0 Gbps |
| General Purpose I/Os (GPIOs) | 875 Mbps LVDS (receiver), 840 Mbps LVDS (transmitter) |
| External Memory Interface | 400 MHz/800 Mbps |
| I/O Voltage Support | 3.3-V at up to 16 mA drive strength |
| Memory Blocks | M10K, 10-Kbit with soft ECC |
| Memory Logic Array Block (MLAB) | 640-bit distributed LUTRAM |
The core voltage is 1.1-V.
Cyclone V devices support integrated transceivers from 614 Mbps to 5.0 Gbps.
Supported protocols include PCIe Gen1 and Gen2, XAUI, GbE, SRIO, CPRI, and others from 614 Mbps to 5.0 Gbps.