This is the data sheet for HardCopy II devices from Altera Corporation, which introduces the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, power consumption reference and ordering information for HardCopy II devices
This document provides data sheet specifications for the HardCopy II device family of low-cost, high-performance structured ASICs. These devices are designed to complement Stratix II FPGAs by offering pin-compatible architectures with equivalent features such as phase-locked loops (PLLs), memory, and I/O elements.
The section details the internal architecture, configuration, JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, power consumption references, and ordering information. It highlights key features including up to 3,600,000 usable gates, support for various high-speed I/O standards like LVDS and HyperTransport, and migration paths from Stratix II FPGA prototypes.
| Process Technology | 1.2 V, 90 nm all-layer-copper metal fabrication process |
|---|---|
| Maximum System Performance | 350 MHz |
| Total RAM Bits (Max) | 8,847,360 bits |
| Maximum User I/O Pins | 951 pins |
HardCopy II structured ASICs offer up to 90% cost reduction compared to Stratix II FPGA prototypes.
Yes, they are pin-compatible, allowing them to serve as drop-in replacements for the FPGAs.
Approximately 10 to 12 weeks.