Altera Stratix & Stratix GX Devices SFI-4 Implementation Manual

Describes the implementation of the SFI-4 interface on altera devices


Altera Stratix & Stratix GX Devices SFI-4 Implementation Manual - cover page
Brand
Altera
Category
Other Electronics
Document type
Application Note
Language
English
Pages
14
File format
PDF
File size
190 KB
Published
01 August, 2012
Updated
30 September, 2023
MD5 checksum
B69AB4D008248D5C62F6397BC42E2F72

About this manual

This chapter focuses on implementing the SFI-4 interface, which connects the SERDES and framer in OC-192 SONET systems. The Optical Internetworking Forum (OIF) standard SFI-4 is a 16-bit LVDS interface used to link the framer and the serializer/deserializer (SERDES). Stratix and Stratix GX devices support the required data rates of up to 622.08 Mbps along with the one-to-one relationship required between clock frequency and data rate.

The document describes the system topology, including the use of 16 channels of source-synchronous LVDS. It details the interface implementation using embedded SERDES circuitry and fast phase-locked loops (PLL) to support high clock frequencies. The text covers both the transmitter and receiver blocks, explaining how parallel data is converted to serial data and vice versa, and how clocks are generated and managed within the Stratix and Stratix GX devices.

What's inside

  • Introduction
  • System Topology
  • Interface Implementation
  • Transmitter Block
  • Receiver Block
  • Clock Generation
  • Data Rates
  • SONET/SDH Standards

Specifications

Data Rate622.08 Mbps
Clock Frequency622.08 MHz or 311.04 MHz
Interface Type16-bit LVDS
Supported DevicesStratix & Stratix GX

Frequently asked questions

What is the SFI-4 interface?

SFI-4 is a 16-bit LVDS interface used in an OC-192 SONET system to link the framer and the serializer/deserializer (SERDES).

How does the Stratix device handle the SFI-4 interface?

The device uses embedded SERDES circuitry and a fast PLL to support the high clock frequencies and one-to-one relationship between clock and data rate.

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