Altera Arria GX Device Handbook Volume 1

About this manual

This document serves as a technical reference for the Altera Arria GX device family. It provides an overview of the device features and detailed architectural descriptions of key blocks including transceivers, logic arrays, adaptive logic modules, memory resources, digital signal processing blocks, and clock networks.

The handbook also covers configuration methods such as JTAG boundary-scan support, SignalTap embedded logic analyzer usage, and various configuration schemes. Additionally, it details DC electrical characteristics, switching parameters, timing models for different I/O standards, power consumption data, and ordering information.

What's inside

• Arria GX Device Family Overview
• Transceiver Architecture
• Logic Array Blocks (LAB)
• Adaptive Logic Modules (ALM)
• Memory Resources (RAM/M-RAM)
• Digital Signal Processing Block
• Clock Networks and PLLs
• I/O Structure and Timing
• Configuration and Testing
• DC and Switching Characteristics

Specifications

Frequently asked questions

What software version is covered in this handbook?

This document covers Software Version 9.1.

When was the content of this handbook published?

The document date is December 2009.