Altera Arria II Device Family Pin Connection Guidelines

About this manual

This document serves as a set of recommendations for connecting pins on Altera Arria II programmable logic devices. It is not a formal specification and should be verified against the specific device datasheet and Quartus II software for any particular design.

The guidelines detail the usage and connection requirements for various pin types, including dedicated clock inputs and outputs, PLL feedback pins, and general I/O pins. Specific instructions are provided for handling unused pins, such as connecting them to ground or using software programmable options to bias them internally.

What's inside

• Pin Connection Guidelines Agreement
• Clock and PLL Pins
• Configuration ITAG Pins
• Unused Pin Handling
• Dedicated Clock Inputs
• Differential Clock Inputs
• PLL Clock Outputs
• Feedback Input Pins

Specifications

Frequently asked questions

Are these pin connection guidelines a formal specification?

No, these guidelines should only be used as a recommendation, not as a specification.

How should unused clock pins be handled?

Unused clock input pins should be connected to ground (GND).

Can unused PLL clock output pins be used as user I/O?

Yes, when not used as clock outputs, these pins may be used as user I/O.