Altera External Memory Interface Handbook Volume 2 Board Planning

About this manual

This document serves as a technical guide for designing board layouts for external memory interfaces. It focuses on improving signal integrity for DDR2 and DDR3 SDRAM systems by addressing leveling, dynamic on-die termination (ODT), output driver impedance, and loading effects. The text compares various termination schemes and their impact on signal quality at the receiver.

What's inside

• DDR2 and DDR3 SDRAM Interface Termination
• Leveling and Dynamic ODT
• Board Termination for DDR2 SDRAM
• Board Termination for DDR3 SDRAM
• Drive Strength and System Loading
• QDRII SDRAM Interface Termination
• RLDRAM II Interface Termination
• Power Estimation Methods
• PCB Layout Guidelines
• Document Revision History

Specifications

Frequently asked questions

What is the objective of this chapter?

The objective is to understand trade-offs between termination schemes, output drive strengths, and loading types to choose the best settings for designs.

What is the purpose of this handbook?

This chapter provides guidelines on how to improve signal integrity and layout instructions for implementing a DDR2 or DDR3 SDRAM interface.

Why must board designers pay closer attention to signal quality?

Poorly transmitted signals can dramatically reduce the overall data-valid margin at the receiver.