This document is about the configuration of Altera Corporation's Cyclone II devices. It describes the configuration schemes used by Cyclone II devices, including active serial, passive serial, and JTAG configuration schemes. It also includes the configuration file format and configuration pin descriptions. Cyclone II devices can use compressed configuration bitstreams to reduce storage requirements and configuration time.
This document explains the configuration features of Cyclone II devices, which use volatile SRAM cells and require data download upon power-up. It details the supported configuration schemes: Active Serial (AS), Passive Serial (PS), and Joint Test Action Group (JTAG)-based configuration, along with the specific MSEL pin settings required for each.
| Configuration Clock Frequency (AS) | up to 40 MHz |
|---|---|
| Configuration Clock Frequency (AS) | 20 MHz |
| Configuration Clock Frequency (Fast AS) | 40 MHz |
| Configuration Data Compression Reduction | 35 to 55% |
Yes, Cyclone II devices support receiving and decompressing configuration bitstreams on-the-fly to reduce storage and time.
You select the scheme by driving the MSEL pins high or low; for example, MSEL1=0 and MSEL0=0 selects AS (20 MHz).