The Cyclone II architecture is a two-dimensional row and column-based architecture used to implement custom logic. The logic array consists of logic elements (LEs), with 16 LEs in each array. Cyclone II devices feature a global clock network and up to four phase-locked loops (PLLs). M4K memory blocks are true dual-port memory blocks with 4K bits of memory plus parity. These features make Cyclone II devices powerful programmable logic devices.
This chapter details the two-dimensional row- and column-based architecture of Cyclone II devices. It explains how Logic Array Blocks (LABs) are grouped into rows and columns to implement custom logic using Logic Elements (LEs), embedded memory blocks, and embedded multipliers. The text covers the global clock network and phase-locked loops (PLLs) available in these devices.
| Logic Elements per LAB | 16 |
|---|---|
| Global clock lines | up to 16 |
| Phase-locked loops | up to four |
| M4K memory bits | 4,608 |
| M4K memory width | up to 36-bits |
| M4K memory speed | up to 260 MHz |
| Embedded multipliers | two 9 x 9-bit or one 18 x 18-bit |
| Embedded multiplier speed | up to 250-MHz |
| I/O data rate | 805 Mbps input / 640 Mbps output |
Cyclone II devices can contain up to 68,416 logic elements.
M4K memory blocks can operate at up to 260 MHz.