Altera Basestation Channel Card Design Guide

This document discusses the technology of designing basestation channel cards, and how Altera's 28-nm FPGA and ASIC technology, along with software tools, development boards, IP, and reference designs, enable future-proof and differentiated designs.


Altera Basestation Channel Card Design Guide - cover page
Brand
Altera
Category
Other Electronics
Document type
Product Leaflet
Language
English
Pages
2
File format
PDF
File size
131 KB
Published
01 August, 2012
Updated
29 September, 2023
MD5 checksum
76B64591CCEC8428957CEBA152F201A6

About this manual

Altera's broad portfolio of 28-nm FPGAs and ASICs, combined with productivity-enhancing software tools and reference designs, supports the development of scalable and differentiated basestation channel cards. The technologies address emerging 4G wireless standards like LTE-Advanced and disruptive network architectures such as baseband pooling for C-RAN and small cells.

What's inside

  • Basestation channel card technology
  • FPGA and ASIC platforms
  • Productivity-enhancing tools
  • LTE PUSCH uplink bitrate reference design
  • LTE symbol rate blocks
  • Layer 2 hardware acceleration
  • Timing and synchronization cores
  • Connectivity cores

Frequently asked questions

What wireless standards does this channel card technology address?

The technology addresses emerging 4G wireless standards such as LTE-Advanced.

Which FPGA platforms are used for switching in macro basestations?

Stratix V GS and GX FPGAs are used for switching/bridging in macro basestation.

What interfaces does the Altera ecosystem offer for connectivity cores?

The suite offers commodity interfaces such as CPRI, OBSAI, SRIO, PCIe, and GigE.

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