This document introduces the simplified interfaces of Altera's DDR, DDR2, and DDR3 SDRAM controllers with ALTMEMPHY IP, as well as their read and write operations to memory devices.
The document describes the Altera DDR, DDR2, and DDR3 SDRAM Controllers with ALTMEMPHY IP. These controllers provide simplified interfaces to industry-standard memory devices by instantiating an ALTMEMPHY megafunction that handles read and write operations between the controller and memory. The system includes a high-performance controller II (HPC II) offering advanced features like configurable command look-ahead and integrated error correction coding.
| Supported Protocols | DDR, DDR2, and DDR3 SDRAM |
|---|---|
| Interface Type | Half-rate or Full-rate |
| ECC Support (DDR/DDR2) | 72-bit |
| ECC Support (DDR3) | 16, 24, and 40-bit |
The controller supports Arria II GX devices with Final support.
No, it only supports half-rate mode for DDR3 SDRAM interfaces.