Altera FPGA Configuration Handbook (Complete Two-Volume Set)

About this manual

The document is a comprehensive two-volume handbook detailing the configuration processes for a wide range of Altera Field-Programmable Gate Arrays (FPGAs). Volume 1 focuses on specific device families including Stratix V, IV, III, II, GX, Cyclone IV, III, I/II, Arria II, GX, APEX II, and legacy devices like Mercury and FLEX 10K. It provides instructions for executing configuration schemes such as Fast Passive Parallel (FPP), Active Serial (AS), Passive Serial (PS), and JTAG.

What's inside

• Configuration Features
• Power-On Reset Circuit
• Configuration Schemes
• Fast Passive Parallel Configuration
• Active Serial Configuration
• Passive Serial Configuration
• JTAG Configuration
• Design Security
• Remote System Upgrades
• Device Configuration Pins

Specifications

Frequently asked questions

Do Stratix V devices support design security?

Yes, design security using configuration bitstream encryption is available in Stratix V devices.

What is the minimum and maximum delay for the fast power-on reset in Stratix V devices?

The fast power-on reset delay ranges from a minimum of 4 ms to a maximum of 12 ms.

What voltage levels are supported for the Vecpdm pin in Stratix V devices?

The supported configuration voltages for the Vecpdm pin are 1.8, 2.5, and 3.0 V.

What voltage must the Vccpp pin be connected to for Stratix V devices?

The Vccpp pin must be connected to 3.0 V or 2.5 V to power the I/O pre-drivers and JTAG I/O pins.