This paper describes how to enhance the power handling capability of the SuperSOTTM-3 Power MOSFET by optimizing the design of copper mounting pads. This design reduces thermal resistance and improves power performance.
This document provides methods to maximize the power handling capability of Fairchild Semiconductor's SuperSOT-3 (SOT-23) Power MOSFETs. It focuses on optimizing copper mounting pad design on circuit boards to reduce thermal resistance and improve performance in natural cooling scenarios without heatsinks.
The text analyzes the relationship between copper pad area, placement (top, bottom, or split), and junction-to-ambient thermal resistance. It concludes that enlarging the copper pad to 0.02 square inches directly under the package on the top side of the board is the most cost-effective approach, increasing maximum power dissipation from approximately 0.46W to 0.6W.
A 0.02 square inch copper pad on the top side of the board can achieve approximately 0.6W.
Increasing the top-side copper pad from 0.001 to 0.02 square inches results in a 30% increase.
The maximized copper lead frame reduces the junction-to-case thermal resistance to 75°C/W.