74F112 is a dual J-K negative edge-triggered flip-flop produced by Philips Semiconductors. It has individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. When the SD and RD inputs are low, they set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A high level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is high and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn.
