74F112 is a dual J-K negative edge-triggered flip-flop produced by Philips Semiconductors. It has individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. When the SD and RD inputs are low, they set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A high level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is high and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn.
This document is a product specification for the Philips 74F112, a dual negative edge-triggered JK-type flip-flop. It features individual J, K, Clock, Set, and Reset inputs with true and complementary outputs. The device is available in commercial and industrial temperature ranges and is offered in 16-pin plastic DIP and SO packages.
| Supply Voltage (VCC) | 4.5V to 5.5V |
|---|---|
| Operating Temperature (Commercial) | 0°C to +70°C |
| Operating Temperature (Industrial) | -40°C to +85°C |
| Supply Current (Total) | 15 mA |
The device features individual J, K, Clock (CP n), Set (S D) and Reset (R D) inputs.
Output changes are initiated by the High-to-Low transition of the CP n input.
When Low, the Set or Reset inputs set or reset the outputs regardless of the level at the other inputs.