PHILIPS 74F113 Dual J-K negative edge-triggered flip-flops without reset handbook

The 74F113 is a dual negative edge-triggered JK-type flip-flop manufactured by Philips Semiconductors. It features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. When the asynchronous SD input is low, it forces the outputs to the steady state levels shown in the function table, regardless of the level at the other inputs. When the clock (CP) input is high, the J and K inputs are enabled and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high, and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP.

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