The 74F113 is a dual negative edge-triggered JK-type flip-flop manufactured by Philips Semiconductors. It features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. When the asynchronous SD input is low, it forces the outputs to the steady state levels shown in the function table, regardless of the level at the other inputs. When the clock (CP) input is high, the J and K inputs are enabled and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high, and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP.
This document is a product specification for the Philips 74F113, which is a dual J-K negative edge-triggered flip-flop without reset. It provides comprehensive details on features, pin configurations, logic diagrams, function tables, and operating modes.
The datasheet includes specific electrical characteristics for both DC and AC parameters under various test conditions, including supply voltage ranges from 4.5V to 5.5V and temperature ranges covering commercial (0°C to +70°C) and industrial (-40°C to +85°C) applications. It also details absolute maximum ratings and ordering information for different package types.
| Supply Voltage (VCC) | 4.5 to 5.5 V |
|---|---|
| Operating Temperature Range (Industrial) | -40°C to +85 °C |
| Maximum Clock Frequency (fmax) | 100 MHz |
| Supply Current (Total) | 21 mA |
Output changes are initiated by the high-to-low transition of the CP (clock) input.
The typical maximum clock frequency for the 74F113 is 100 MHz.