Mosaic PUMA 2E1000-70/90/12/X405 1Mbit CMOS EEPROM Datasheet

This document is about the query service for the PUMA2E1000-10 supplier. The product has specific features and characteristics.


Mosaic PUMA 2E1000-70/90/12/X405 1Mbit CMOS EEPROM Datasheet - cover page
Brand
Mosaic
Category
Memory
Document type
Datasheet
Language
English
Pages
12
File format
PDF
File size
467 KB
Published
05 July, 2012
Updated
28 September, 2023
MD5 checksum
050CF4A911313F0FA86648AE8D328C26

About this manual

The PUMA 2E1000/X405 is a 1Mbit CMOS High Speed EEPROM organized as 32K x 32. It is available in a 66 pin PGA package suitable for thermal ladder applications. The device offers access times of 70ns, 90ns, or 120ns and features user-configurable output width of 8, 16, or 32 bits.

What's inside

  • Description
  • Features
  • DC Operating Conditions
  • AC Read Characteristics
  • Write Cycle
  • Page Mode Write Cycle
  • DATA Polling Characteristics
  • Toggle Bit Characteristics
  • Device Operation
  • Chip Erase Waveform

Specifications

Memory Capacity1Mbit (32K x 32)
Package Type66 pin PGA
Access Times70ns, 90ns, or 120ns
Data Retention10 years
Operating Power1760 mW (max)
Standby Power1320 mW (max)
Endurance10^5 Cycles
Operating Temperature Range-55 to +125 °C

Frequently asked questions

What is the data retention time of the PUMA 2E1000?

The device has a data retention time of 10 years.

Can the output width be configured?

Yes, the output width is user configurable as 8, 16, or 32 bits wide.

What are the available access times?

The available access times are 70ns, 90ns, or 120ns.

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