intel 28F128J3A 28F640J3A 28F320J3A (x8/x16) 3 Volt Intel StrataFlash Memory Preliminary Datasheet

About this manual

This document is a preliminary datasheet for Intel's 28F128J3A, 28F640J3A, and 28F320J3A (x8/x16) StrataFlash memory devices. These products utilize a high-density symmetrically-blocked architecture with erase blocks of 128 Kbytes in densities ranging from 32 Mbit to 128 Mbit.

What's inside

• Product Overview
• Principles of Operation
• Bus Operations
• Command Definitions
• Design Considerations
• Electrical Specifications
• Ordering Information

Specifications

Frequently asked questions

What is the technology generation of this memory?

The devices utilize Intel's 0.25 micron ETOX™ VI process technology.

What voltage range is required for the 28F128J3A, 28F640J3A, and 28F320J3A memory devices?

These devices operate with a Vcc voltage between 2.7 V and 3.6 V.

What is the minimum number of erase cycles supported by the 128 Mbit, 64 Mbit, and 32 Mbit versions?

The 128 Mbit version supports 12.8M cycles, the 64 Mbit version supports 6.4M cycles, and the 32 Mbit version supports 3.2M cycles.

What is the effective programming time per byte for these memory devices?

The effective programming time is 6 us per byte.