This data sheet introduces the features and characteristics of µPD45128441, 45128841, 45128163 128M-bit Synchronous DRAM 4-bank, LVTTL
This document is a datasheet for the NEC uPD45128441, uPD45128841, and uPD45128163, which are high-speed 128M-bit synchronous dynamic random-access memories. These devices are organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4, and 2,097,152 x 16 x 4 (word x bit x bank), respectively. They utilize a pipeline architecture to achieve high-speed data transfer with all inputs and outputs synchronized to the positive edge of the clock.
| Memory Density | 128M-bit |
|---|---|
| Organization | 8,388,608 x 4 x 4 |
| Number of Banks | 4 banks |
| Interface | LVTTL |
| Package Type | 54-pin TSOP (II) |
| Power Supply | 3.3 V + 0.3 V |
| Refresh Cycles | 4,096 / 64 ms |
The uPD45128441 is organized as 8,388,608 x 4 x 4.
The uPD45128841 is organized as 4,194,304 x 8 x 4.
The uPD45128163 is organized as 2,097,152 x 16 x 4.
These products are packaged in 54-pin TSOP (II).