This data sheet describes the features of STE10/100A PCI Fast Ethernet controller, including speed and duplex detection, half-duplex and full-duplex operation, full-duplex flow control, long FIFO buffers, early interrupt mechanism.
The STE10/100A is a high-performance PCI Fast Ethernet controller featuring an integrated physical layer interface for 10BASE-T and 100BASE-TX applications. It utilizes advanced CMOS technology to provide a glueless 32-bit bus master interface for the PCI bus, along with support for CSMA/CD protocols and auto-negotiation for speed and duplex detection.
Key features include both half-duplex and full-duplex operation, long FIFO buffers for transmission and receiving, and an early interrupt mechanism to enhance performance. The device supports ACPI and PCI compliant power management functions and is available in a 128-pin QFP package.
| Interface Standard | IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant |
|---|---|
| Package Type | 128-pin QFP package |
| Operating Voltage | 3.3V |
| Clock Frequency Range | 20MHz to 33MHz |
The device comes in a 128-pin QFP package.
Yes, it supports IEEE802.3u Auto-Negotiation for both 10BASE-T and 100BASE-TX.
The controller provides up to 128kB EPROM or Flash-ROM application space.