The MC14043B and MC14044B quad R-S latches are constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has an independent Q output and set and reset inputs. The Q outputs are gated through three-state buffers having a common enable input. The outputs are enabled with a logical “1” or high on the enable input; a logical “0” or low disconnects the latch from the Q outputs, resulting in an open circuit at the Q outputs.
This document provides technical specifications for the MC14043B and MC14044B, which are CMOS MSI Quad R-S Latches. These devices utilize MOS P-channel and N-channel enhancement mode devices in a single monolithic structure to provide independent Q outputs with set and reset inputs.
| Supply Voltage Range | -0.5 to +18.0 Vdc |
|---|---|
| Ambient Temperature Range | -55 to +125 °C |
| Power Dissipation | 500 mW per Package |
| Input Capacitance | 75 pF |
The rated supply voltage range is -0.5 Vdc to +18.0 Vdc.
Yes, the outputs are capable of driving two low-power TTL loads or one low-power Schottky TTL load.
Yes, the Q outputs are gated through three-state buffers having a common enable input.