This document is a guideline for the SPICE device model of SUM110N04-2m7H Vishay Siliconix. It describes the features and characteristics of the product and provides corresponding electrical specification data.
This document presents a SPICE device model for the SUM110N04-2m7H, an N-Channel Vertical DMOS transistor. The model is a Level 3 macro subcircuit optimized for the -55 to 125°C temperature range and includes parameters for gate charge, transient response, and diode reverse recovery. It is intended as a modeling guideline for designers rather than a commercial product specification sheet.
The document provides simulated and measured electrical specifications, including static parameters like on-state resistance and dynamic parameters such as input and output capacitance. It also includes graphical comparisons between the model simulation data and actual measured data for various operating conditions.
| Device Type | N-Channel Vertical DMOS |
|---|---|
| Temperature Range | -55 to 125°C |
| Gate Threshold Voltage (Simulated) | 3.7 V |
| On-State Drain Current (Simulated) | 1170 A |
| Drain-Source On-State Resistance (Simulated) | 0.0022 Ohm |
| Forward Transconductance (Simulated) | 87 S |
| Input Capacitance (Simulated) | 12450 pF |
| Output Capacitance (Simulated) | 1429 pF |
| Total Gate Charge (Simulated) | 262 nC |
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet.
The model uses Level 3 MOS technology.
Yes, the subcircuit model is optimized over the -55 to 125°C temperature ranges.