The CY7C1366B/CY7C1367B 9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM is a high-performance synchronous SRAM chip from Cypress Semiconductor Corporation. It supports a high data transfer rate of 225 MHz and provides multiple packaging options, including JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA, to meet the needs of different application scenarios.
The document details the features of the CY7C1366B (256K x 36) and CY7C1367B (512K x 18) synchronous SRAMs. These devices integrate advanced peripheral circuitry, including a two-bit counter for internal burst operations, and support bus speeds up to 225 MHz with available speed grades of 225, 200, and 166 MHz.
Key features include registered inputs and outputs for pipelined operation, optimal performance via double-cycle deselect, depth expansion without wait states, and a core power supply range of 3.3V -5% to +10%. The devices operate with 3.3V or 2.5V I/O supplies and are offered in JEDEC-standard 100-pin TQFP, 119-ball BGA, and 165-ball fBGA packages.
| Maximum Access Time (225 MHz) | 2.8 ns |
|---|---|
| Maximum Access Time (200 MHz) | 3.0 ns |
| Maximum Access Time (166 MHz) | 3.5 ns |
| Maximum Operating Current (225 MHz) | 250 mA |
| Core Power Supply Range | 3.3V -5% to +10% |
Available speed grades are 225, 200 and 166 MHz.
The maximum access time is 2.8 ns.
It requires a +3.3V core power supply with -5% and +10% tolerance.