This document describes the features and characteristics of the AS7C33128PFS18B product from Alliance Semiconductor. The product is a 3.3V 128K × 18 pipeline burst synchronous static RAM, with fast clock speeds, fast clock to data access time, and fully synchronous register-to-register operation.
The AS7C33128PFS18B is a high-performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words x 18 bits. It incorporates a pipeline architecture designed for highest frequency operation and features fast clock speeds up to 200 MHz with access times of 3.0/3.5/4.0 ns.
The device supports multiple chip enables for easy memory expansion and offers flexible burst control via linear or interleaved sequences selectable by the LBO input. It operates from a 3.3V core power supply with I/Os that can run at either 2.5V or 3.3V, available in a 100-pin TQFP package.
| Organization | 131,072 words x 18 bits |
|---|---|
| Core Power Supply | 3.3V |
| Maximum Clock Frequency | 200 MHz |
| Clock Access Time | 3.0/3.5/4.0 ns |
| Package Type | 100-pin TQFP |
The device is organized as 131,072 words x 18 bits.
Yes, it supports 2.5V or 3.3V I/O operation with a separate Vppg supply.
The LBO input selects between linear and interleaved burst orders.