Update: 30 September, 2023
The ICS650-27 is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-27 outputs all have zero ppm synthesis error. The ICS650-27 is pin compatible and functionally equivalent to the ICS650-07. It is a performance upgrade and is recommended for all new 3.3V designs.
File format: PDF
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MD5 Checksum: 9E6B1F7EE47330ECE4F721C141BA9B1A
Publication date: 04 June, 2012
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PDF Link: ICS ICS650-27 Networking Clock Source PDF